CY28331
Document #: 38-07491 Rev. *E
Page 4 of 17
Serial Control Registers
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
11:18
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Byte 0: Frequency and Spread Spectrum Control Register
Bit
@Pup
Pin#
Name
Description
7
Inactive = 0
Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0
bit0 will permanently disable modification of all configuration registers until the part
has been powered off. Once the clock generator has been Write Disabled, the
SMBus controller should still accept and acknowledge subsequent write cycles but
it should not modify any of the registers.
6
0
For Test, always program to ‘0’
5
1
12
PCI33_7
Enable (1 = Enabled, 0 = Disabled)
4
FS3 pin
31
FS3
corresponds to Frequency Selection. See Table 1.
3
FS2 pin
45
FS2
corresponds to Frequency Selection. See Table 1.
2
FS1 pin
48
FS1
corresponds to Frequency Selection. See Table 1.
1
FS0 pin
1
FS0
corresponds to Frequency Selection. See Table 1.
0
Inactive = 0
Write Enable. A 1 written to this bit after power-up will enable modification of all
configuration registers and subsequent 0's written to this bit will disable modification
of all configuration except this single bit. Note that block write transactions to the
interface will complete, however unless the interface has been previously unlocked,
the writes will have no effect. The effect of writing this bit doe not take effect until
the subsequent block write command.
Byte 1: PCI Clock Control Register
Bit
@Pup
Pin#
Name
Description
7
1
23
PCI33_F
Enable (1 = Enabled, 0 = Disabled)
6
1
24
PCI33_6
Enable (1 = Enabled, 0 = Disabled)
5
1
22
PCI33_5
Enable (1 = Enabled, 0 = Disabled)
4
1
21
PCI33_4
Enable (1 = Enabled, 0 = Disabled)
3
1
18
PCI33_3
Enable (1 = Enabled, 0 = Disabled)
2
1
17
PCI33_2
Enable (1 = Enabled, 0 = Disabled)
1
1
14
PCI33_1
Enable (1 = Enabled, 0 = Disabled)
0
1
13
PCI33_0
Enable (1 = Enabled, 0 = Disabled)
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