CY28330
Document #: 38-07366 Rev. *B
Page 7 of 15
Byte 7: Watchdog Control Register
Bit
@Pup
Name
Description
7
0
Pin 12 Mode
Select
SRESET#; 1 = Pin 12 is the input pin which functions as a PD# signal. 0 = Pin 12 is the
output pin as SRESET# signal.
6
0
Frequency
Reversion
This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog
time out only.
0 = selects frequency of existing H/W setting
1 = selects frequency of the second to last S/W setting. (the software setting prior to the
one that caused a system reboot).
5
0
For Test, ALWAYS program to ‘0’
4
0
WD Time-out
This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears
the WD time stamps (WD3:0).
3
0
WD3
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
2
0
WD2
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9
1
0
WD1
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
0
0
WD0
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
Table 9. Watchdog Time Stamp
WD3
WD2
WD1
WD0
Function
00
00
Off
0
0
0
1
1 second
00
10
2 seconds
00
11
3 seconds
01
00
4 seconds
01
01
5 seconds
01
10
6 seconds
01
11
7 seconds
10
00
8 seconds
10
01
9 seconds
10
10
10 seconds
10
11
11 seconds
11
00
12 seconds
11
01
13 seconds
11
10
14 seconds
11
11
15 seconds
Byte 8: Dial-a-Frequency™ Control Register N
Bit
@PUp
Description
70
ATPG Pulse. A 0 to 1 transition on this bit will trigger a differential pulse on the CPUT/C
lines whose pulse width is equal to the period of the currently latched frequency.
6N6
These bits are for programming the PLL’s internal N register. This access allows the
user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks
that are generated from the same PLL, such as PCI, remain at their existing ratios relative
to the CPU clock.
5N5
4N4
3N3
2N2
1N1
0N0
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