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CY28330
Document #: 38-07366 Rev. *B
Page 11 of 15
Table 12. REF(0:2) Clock Outputs
Parameter
Description
Test Condition
PCI133_HT66 = 66 MHz
Unit
Min.
Typ.
Max.
VOL
Output Low Voltage
IOL = 9.0 mA
0.4
V
VOH
Output High Voltage
IOH = -12.0 mA
2.4
V
IOL
Output Low Current
VO = 0.8V
16
mA
IOH
Output High Current
VO = 2.0V
-22
mA
F
Frequency, Actual
14.318
MHz
TR
Output Rise Edge Rate
Measured from 20% to 60%
0.5
2
V/ns
TF
Output Fall Edge Rate
Measured from 60% to 20%
0.5
2
V/ns
TD
Duty Cycle
Measured at 1.5V
45
55
%
TJC
Jitter, Cycle-to-Cycle
Measured at 1.5V
0
500
1000
ps
TJA
Jitter, Accumulated
Measured at 1.5V
-1000
1000
ps
TFS
Frequency Stabilization from Power-up Measure from full supply voltage
0
3
mS
RON
Output Impedance
Average value during switching transition.
20
24
60
W
Table 13. USB, 24_24 Clock Outputs
Parameter
Description
Conditions
PCI33, PCI33_HT =
33MHz
PCI33_HT = 66MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
VOL
Output Low Voltage
IOL = 9.0mA
0.4
0.4
V
VOH
Output High Voltage
IOH =-12.0mA
2.4
2.4
V
IOL
Output Low Current
VO = 0.8V
16
16
mA
IOH
Output High Current
VO = 2.0V
-22
-22
mA
F
Frequency Actual
24.004
48.008
MHz
TR
Output Rise Edge Rate
Measured from 20% to
80%
0.5
2
0.5
2
V/ns
TF
Output Fall Edge Rate
Measured from 80% to
20%
0.5
2
0.5
2
V/ns
TD
Duty Cycle
Measured at 1.5V
45
55
45
55
%
TJC
Jitter, Cycle-to-Cycle 24_48
MHz
Measured at 1.5V
0
250
500
0
250
500
ps
TJC
Jitter, Cycle-to-Cycle USB
Measured at 1.5V
0
100
ps
TJA
Jitter Accumulated
Measured at 1.5V
-1000
1000
-1000
1000
ps
TFS
Frequency Stabilization from
Power-up
Measure from full supply
voltage
03
0
3
ms
RON
Output Impedance
Average value during
switching transition.
20
24
60
20
24
60
W
Table 14. Skew [5]
Parameter
Description
Conditions
Skew Window Unit
TSK_CPU_CPU
CPU to CPU skew, time
independent
Measured @ crossing points for CPUT rising edges1
250
ps
TSK_CPU_PCI33
CPU to PCI33 skew, time
independent
Measured @ crossing points for CPUT rising edge and
1.5V PCI clocks
500
ps
TSK_PCI33_PCI33 PCI33 to PCI33 skew,
time independent
Measured between rising @ 1.5V
500
ps
Note:
5.
All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between
these two signals to be 500ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either
be 500ps before the CPU clock to 500ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
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