FTG for VIA PL133T and PLE133T
CY28316
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07125 Rev. *B
Revised December 14, 2002
Features
• Single-chip system frequency synthesizer for VIA
PL133T and PLE133T chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Automatically switches to HW-selected or
SW-programmed clock frequency when Watchdog
Timer time-out occurs
• Capable of generating system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Supports SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for SDRAM and PCI
output clocks
• Programmable output skew for CPU, PCI, and SDRAM
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
Note:
1.
Signals marked with ‘*’ have internal pull-up resistors.
Block Diagram
Pin Configuration
[1]
VDD_REF
REF0
PCI0/FS4*
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2*
VDD_PCI
PCI2:6
48MHz/FS0*
24_48MHz/FS1*
PLL2
÷2,3,4
OSC
VTTPWRGD#
VDD_48MHz
SMBus
SDATA
Logic
SCLK
SDRAM0:12
SDRAMIN
13
VDD_SDRAM
PCI1/FS3*
CPU0:1
÷2
VDD_REF
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
VDD_PCI
SDRAMIN
GND_SDRAM
SDRAM11
SDRAM10
VDD_SDRAM
SDRAM9
SDRAM8
GND_SDRAM
SDATA
SCLK
VTT_PWRGD#
REF0
REF1/FS2*
GND_CPU
CPU0
CPU1
VDD_CPU
RST#
SDRAM_12
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
SDRAM6
SDRAM7
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SMBus
{
Logic
Reset
RST#
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