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CY28312B-2
Document #: 38-07596 Rev. **
Page 6 of 17
Bit 2
13
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
10
PCI0
1
(Active/Inactive)
Byte 3: Control Register
Bit
Pin#
Name
Default
Description
Bit 7
9
PCI_F
1
(Active/Inactive)
Bit 6
22
PCI9_E
1
(Active/Inactive)
Bit 5
–
Reserved
0
Reserved
Bit 4
21
PCI8
1
(Active/Inactive)
Bit 3
46
REF2
1
(Active/Inactive)
Bit 2
–
Reserved
0
Reserved
Bit 1
47
REF1
1
(Active/Inactive)
Bit 0
48
REF0
1
(Active/Inactive)
Byte 4: Watchdog Timer Register
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
FS_Override
0
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Bit 5
–
WD_TIMER4
1
These bits store the time-out value of the Watchdog
timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec
when the prescaler is set to 150 ms. If the prescaler is
set to 2.5 sec, it can support a value from 2.5 sec to 80
sec.
When the Watchdog timer reaches “0”, it will set the
WD_TO_STATUS bit.
Bit 4
–
WD_TIMER3
1
Bit 3
–
WD_TIMER2
1
Bit 2
–
WD_TIMER1
1
Bit 1
–
WD_TIMER0
1
Bit 0
–
WD_PRE_SCAL
ER
0
0 = 150 ms
1 = 2.5 sec
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
9
Latched FS4 input
X
Latched FS[4:0] inputs. These bits are read-only.
Bit 6
7
Latched FS3 input
X
Bit 5
6
Latched FS2 input
X
Bit 4
47
Latched FS1 input
X
Bit 3
48
Latched FS0 input
X
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
0
Reserved
Bit 0
–
SEL4
0
SW Frequency selection bits. See Table 4.
Byte 6: Reserved Register
Bit
Name
Default
Description
Bit 7
Reserved
1
Reserved
Bit 6
Reserved
1
Reserved
Bit 5
Reserved
1
Reserved
Bit 4
Reserved
1
Reserved
Byte 2: Control Register 2 (continued)
Bit
Pin#
Name
Default
Description
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