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CY25000 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY25000
Description  Programmable Spread Spectrum Clock Generator for EMI Reduction
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY25000 Datasheet(HTML) 2 Page - Cypress Semiconductor

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CY25000
Document #: 38-07424 Rev. *B
Page 2 of 10
General Description
The CY25000 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Inter-
ference (EMI) found in today’s high-speed digital electronic
systems.
The device uses a Cypress-proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency requirements (EMC) and improve time to
market without degrading system performance.
The CY25000 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %,
crystal load capacitor, reference clock on/off and PD#/OE
options.
The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts if required.
The input to the CY25000 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25000 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same
frequency as the input of the CY25000. The frequency
modulated SSCLK output can be programmed from 3–200
MHz.
The CY25000 products are available in an 8-pin SOIC
(150-mil) package with a commercial operating temperature
range of 0 to 70
°C.
Pin Descriptions
Pin
Name
Description
1
XIN/CLKIN
Crystal input or reference clock input.
2VDD
3.3V voltage supply.
3
PD#/OE
Power-down pin. Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.
4
VSS
GND.
5
SSCLK
Spread spectrum clock output.
6REFCLK
Buffered reference output.
7
SSON
Spread spectrum control. 1 = Spread on. 0 = Spread off.
8XOUT
Crystal output. Leave this pin floating if external clock is used.


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