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MediaClock™
DTV, STB Clock Generator
CY24204
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07450 Rev. *C
Revised January 19, 2005
Features
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with Analog Adjust
• 3.3V operation
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Large ±150-ppm range, better linearity
• Enables application compatibility
Part Number Outputs
Input Frequency
Output Frequency Range
CY24204-3
4
27-MHz Crystal Input
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable)
CY24204-4
4
27-MHz Crystal Input
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable,
Increased VCXO pull range)
CY24204-5
4
27-MHz Crystal Input
Two copies of 27-MHz reference clock output, two copies of
27/27.027/74.250/74.17582418 MHz (frequency selectable,
Increased output drive strength)
Block Diagram
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLK1
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
FS0
FS1
CLK2
REFCLK1
VSSL
VDD
Pin Configurations
OE
VCXO
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
FS0
XIN
XOUT
VDD
VCXO
AVSS
REFCLK1
OE
FS1
AVDD
VDDL
CLK2
CLK1
REFCLK2
REFCLK2
(-3,-4,-5)
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