4 / 8 page
CY2310ANZ
Document #: 38-07142 Rev. *B
Page 4 of 8
Switching Characteristics[3]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Maximum Operating Frequency
100
MHz
Duty Cycle[2, 4] = t2 ÷ t1
Measured at 1.5V
45.0
50.0
55.0
%
t3
Rising Edge Rate[2]
Measured between 0.4V and 2.4V
0.9
1.5
4.0
V/ns
t4
Falling Edge Rate[2]
Measured between 2.4V and 0.4V
0.9
1.5
4.0
V/ns
t5
Output to Output Skew[2]
All outputs equally loaded
150
250
ps
t6
SDRAM Buffer LH Prop. Delay[2]
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
t7
SDRAM Buffer HL Prop. Delay[2]
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
t8
SDRAM Buffer Enable Delay[2]
Input edge greater than 1 V/ns
1.0
5
12
ns
t9
SDRAM Buffer Disable Delay[2]
Input edge greater than 1 V/ns
1.0
20
30
ns
Switching Waveforms
Notes:
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns
Duty Cycle Timing
t1
t2
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t4
Output-Output Skew
1.5V
t5
OUTPUT
OUTPUT
1.5V