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CY2292 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY2292
Description  Three-PLL General-Purpose EPROM Programmable Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY2292 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY2292
Document #: 38-07449 Rev. *C
Page 6 of 11
t9A
Clock Jitter[14]
Peak-to-peak period jitter (t9A max. – t9A
min.), % of clock period (fOUT < 4 MHz)
<0.5
1
%
t9B
Clock Jitter[14]
Peak-to-peak period jitter (t9B max. – t9B
min.)
(4 MHz < fOUT < 16 MHz)
<0.7
1
ns
t9C
Clock Jitter[14]
Peak-to-peak period jitter (16 MHz < fOUT <
50 MHz)
<400
500
ps
t9D
Clock Jitter[14]
Peak-to-peak period jitter (fOUT > 50 MHz)
<250
350
ps
t10A
Lock Time for CPLL
Lock Time from Power-up
<25
50
ms
t10B
Lock Time for UPLL and
SPLL
Lock Time from Power-up
<0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2292
20
100
MHz
CY2292F
20
90
MHz
Switching Characteristics, Commercial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 3.3V
operation
CY2292
12.5
(80 MHz)
13000
(76.923 kHz)
ns
CY2292F
15
(66.6 MHz)
13000
(76.923 kHz)
ns
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHz
40%
50%
60%
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHz
45%
50%
55%
t3
Rise Time
Output clock rise time[13]
35
ns
t4
Fall Time
Output clock fall time[13]
2.54ns
t5
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
10
15
ns
t6
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
ns
t7
Skew
Skew delay between any identical or related
outputs[3, 12, 14]
< 0.25
0.5
ns
t8
CPUCLK Slew
Frequency transition rate
1.0
20.0
MHz/
ms
t9A
Clock Jitter[14]
Peak-to-peak period jitter (t9A max. – t9A min.),
% of clock period (fOUT < 4 MHz)
< 0.5
1
%
t9B
Clock Jitter[14]
Peak-to-peak period jitter (t9B max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
< 0.7
1
ns
t9C
Clock Jitter[14]
Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz)
< 400
500
ps
t9D
Clock Jitter[14]
Peak-to-peak period jitter (fOUT > 50 MHz)
< 250
350
ps
t10A
Lock Time for CPLL Lock Time from Power-up
< 25
50
ms
t10B
Lock Time for
UPLL and SPLL
Lock Time from Power-up
< 0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2292
20
80
MHz
CY2292F
20
66.6
MHz
Switching Characteristics, Commercial 5.0V (continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit


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