10 / 14 page
CY2291
Document #: 38-07189 Rev. *A
Page 10 of 14
Switching Characteristics, Industrial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 3.3V
operation
CY2291I
15
(66.6 MHz)
13000
(76.923 kHz)
ns
CY2291FI
16.66
(60 MHz)
13000
(76.923 kHz)
ns
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1
[12]
fOUT > 66 MHZ
40%
50%
60%
Duty cycle for outputs, defined as t2 ÷ t1
[12]
fOUT < 66 MHZ
45%
50%
55%
t3
Rise Time
Output clock rise time[13]
35
ns
t4
Fall Time
Output clock fall time[13]
2.5
4
ns
t5
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
10
15
ns
t6
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
ns
t7
Skew
Skew delay between any identical or related out-
puts[3, 12, 15]
< 0.25
0.5
ns
t8
CPUCLK Slew
Frequency transition rate
1.0
20.0
MHz/
ms
t9A
Clock Jitter[14]
Peak-to-peak period jitter (t9A Max. – t9A min.),%
of clock period (fOUT < 4 MHz)
<0.5
1
%
t9B
Clock Jitter[14]
Peak-to-peak period jitter (t9B Max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
<0.7
1
ns
t9C
Clock Jitter[14]
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
<400
500
ps
t9D
Clock Jitter[14]
Peak-to-peak period jitter
(fOUT > 50 MHz)
<250
350
ps
t10A
Lock Time for
CPLL
Lock Time from Power-Up
<25
50
ms
t10B
Lock Time for
UPLL and SPLL
Lock Time from Power-Up
<0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2291I
8
66.6
MHz
CY2291FI
8
60
MHz
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1
OUTPUT
t2
t3
t4
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
