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CY2077 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY2077
Description  High-accuracy EPROM Programmable Single-PLL Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY2077 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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CY2077
Document Number: 38-07210 Rev. *C
Page 3 of 14
Power Management Features
PWR_DWN and OE options are configurable by EPROM
programming for the CY2077. In PWR_DWN mode, all active
circuits are powered down when the control pin is set LOW.
When the control pin is set back HIGH, both the PLL and oscil-
lator circuit must relock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is set
LOW. The oscillator and PLL are still active in this state, which
leads to a quick clock output return when the control pin is set
back HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT
immediately (allowing for logic delays), without respect to the
current state of CLKOUT. Synchronous mode prevents output
glitches by waiting for the next falling edge of CLKOUT after
PWR_DWN, or OE becomes asserted. In either asynchronous
or synchronous setting, the output is always enabled synchro-
nously by waiting for the next falling edge of CLKOUT.
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage .................................................. –0.5 to +7.0V
Input voltage ........................................... –0.5V to VDD +0.5V
Storage temperature (non-condensing)...... –55°C to +150°C
Junction temperature.................................................. 150°C
Static discharge voltage........................................... > 2000V
(per MIL-STD-883, method 3015)
Operating Conditions for Commercial Temperature Device
Table 3. Device Functionality: Output Frequencies
Symbol
Description
Condition
Min
Max
Unit
Fo
Output frequency
VDD = 4.5–5.5V
0.39
133
MHz
VDD = 3.0–3.6V
0.39
100
MHz
Parameter
Description
Min
Max
Unit
VDD
Supply voltage
3.0
5.5
V
TA
Operating temperature, ambient
0
+70
°C
CTTL
Max. capacitive load on outputs for TTL levels
VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz
VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz
VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz
50
25
15
pF
pF
pF
CCMOS
Max. capacitive load on outputs for CMOS levels
VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz
VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz
VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz
VDD = 3.0 – 3.6V, output frequency = 1 – 40 MHz
VDD = 3.0 – 3.6V, output frequency = 40 – 100 MHz
50
25
15
30
15
pF
pF
pF
pF
pF
XREF
Reference frequency, input crystal with Cload = 10 pF
10
30
MHz
Reference frequency, external clock source
1
75
MHz
tPU
Power up time for all VDD's to reach minimum specified voltage (power ramps must
be monotonic)
0.05
50
ms
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