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CY2077 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY2077
Description  High-accuracy EPROM Programmable Single-PLL Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY2077 Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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CY2077
Document Number: 38-07210 Rev. *C
Page 5 of 14
Output Clock Switching Characteristics Commercial
Over the Operating Range[4]
Parameter
Description
Test Conditions
Min
Typ
Max Unit
t1w
Output duty cycle at 1.4V,
VDD = 4.5 – 5.5V
t1w = t1A ÷ t1B
1 – 40 MHz, CL <= 50 pF
40 – 125 MHz, CL <= 25 pF
125 – 133 MHz, CL <= 15 pF
45
45
45
55
55
55
%
%
%
t1x
Output duty cycle at VDD/2,
VDD = 4.5 – 5.5V
t1x = t1A ÷ t1B
1 – 40 MHz, CL <= 50 pF
40 – 125 MHz, CL <= 25 pF
125 – 133 MHz, CL <= 15 pF
45
45
45
55
55
55
%
%
%
t1y
Output duty cycle at VDD/2,
VDD = 3.0 – 3.6V
t1y = t1A ÷ t1B
1 – 40 MHz, CL <= 30 pF
40 – 100 MHz, CL <= 15 pF
45
40
55
60
%
%
t2
Output clock rise time
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 50 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 25 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF
Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 50 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 30 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t3
Output clock fall time
Between 0.8V –2.0V, VDD = 4.5V – 5.5V, CL = 50 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 25 pF
Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF
Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 50 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 30 pF
Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t4
Start-up time out of power
down
PWR_DWN pin LOW to HIGH[5]
12
ms
t5a
Power down delay time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T= period of output CLK)
T/2
T +
10
ns
t5b
Power down delay time
(asynchronous setting)
PWR_DWN pin LOW to output LOW
10
15
ns
t6
Power up time
From power on[5]
12
ms
t7a
Output disable time
(synchronous setting)
OE pin LOW to output high-Z
(T= period of output CLK)
T/2
T +
10
ns
t7b
Output disable time
(asynchronous setting)
OE pin LOW to output high-Z
10
15
ns
t8
Output enable time
(always synchronous
enable)
OE pin LOW to HIGH
(T= period of output CLK)
T1.5T
+
25ns
ns
t9
Peak-to-peak period
jitter
VDD = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, VCO > 100 MHz
VDD = 3.0V – 5.5V, Fo < 33 MHz
80
0.3%
150
1%
ps
% of
FO
Notes
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70
Ω.
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