CY27EE16ZE
Document #: 38-07440 Rev. *C
Page 4 of 17
CY27EE16ZE Frequency Calculation and
Register Definitions
The CY27EE16ZE is an extremely flexible clock generator
with four basic variables that can be used to determine the final
output frequency. They are the input reference frequency
(REF), the internally calculated P and Q dividers, and the post
divider, which can be a fixed or calculated value. There are
three basic formulas for determining the final output frequency
of a CY27EE16ZE-based design. Any one of these three
formulas may be used:
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
The basic PLL block diagram is shown in Figure 2. Each of the
six clock outputs on the CY27EE16ZE has a total of seven
output options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
reference frequency directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the reference frequency
directly to the crosspoint switch matrix.
Table 1. Summary Table – CY27EE16ZE Programmable Registers
Register Description
D7D6D5D4D3D2D1D0
09H
CLKOE control
0
CLOCK6
CLOCK5
0
CLOCK4
CLOCK3
CLOCK2
CLOCK1
OCH
DIV1SRC mux and
DIV1N divider
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
10H
Input Pin Control
Registers
OESrc
OE0PadS
el[1]
OE0PadS
el[0]
OE1PadS
el[1]
OE1PadS
el[0]
PDMEna-
ble
PDMPad-
Sel[1]
PDMPad-
Sel[0]
11H
Write Protect
Registers
MemWP
WPSrc
WPPad-
Sel[2]
WPPad-
Sel[1]
WPPad-
Sel[0]
12H
Input crystal oscillator
drive control
FTAAd-
drSrc(1)
default=0
FTAAd-
drSrc(0)
default=0
XCapSrc
default=1
XDRV(1)
XDRV(0)
0
0
0
13H
Input load capacitor
control
Cap-
Load(7)
Cap-
Load(6)
Cap-
Load(5)
Cap-
Load(4)
Cap-
Load(3)
Cap-
Load(2)
Cap-
Load(1)
Cap-
Load(0)
14H
ADC Register
ADCEn-
able
AD-
CBypCnt
ADC-
Cnt[2]
ADC-
Cnt[1]
ADC-
Cnt[0]
ADCFilt[1] ADCFilt[0]
0
40H
Charge Pump and PB
counter
1
1
0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
41H
PB(7)
PB(6)
PB(5)
PB(4)
PB(3)
PB(2)
PB(1)
PB(0)
42H
PO counter, Q
counter
PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
44H
Crosspoint switch
matrix control
CLKSRC2
for
CLOCK1
CLKSRC1
for
CLOCK1
CLKSRC0
for
CLOCK1
CLKSRC2
for
CLOCK2
CLKSRC1
for
CLOCK2
CLKSRC0
for
CLOCK2
CLKSRC2
for
CLOCK3
CLKSRC1
for
CLOCK3
45H
CLKSRC0
for
CLOCK3
CLKSRC2
for
CLOCK4
CLKSRC1
for
CLOCK4
CLKSRC0
for
CLOCK4
111
CLKSRC2
for
CLOCK5
46H
CLKSRC1
for
CLOCK5
CLKSRC0
for
CLOCK5
CLKSRC2
for
CLOCK6
CLKSRC1
for
CLOCK6
CLKSRC0
for
CLOCK6
111
47H
DIV2SRC mux and
DIV2N divider
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
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