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PRELIMINARY
CY28RS480-1
Document #: 38-07714 Rev. *C
Page 9 of 16
CLK_STOP
When CLK_STOP is sampled HIGH by two consecutive rising
edges of CPUC, all single-ended outputs must be held LOW
on their next HIGH-to-LOW transition and differential clocks
must held LOW on the next diff clock# HIGH-to-LOW
transition. This diagram and description is applicable to valid
CPU frequencies
.
CLK_STOP
USB, 48MHz
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 4. CLK_STOP Assertion Timing Waveform
CPU_CLOCK
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
SRCT 100MHz
Tstable
< 2
REFCLK
PCI, 33MHz
REF
Tdrive_PWRDN#
<300
µS, >200mV
Figure 5. CLK_STOP Deassertion Timing Waveform