CY23FS04
Document #: 38-07304 Rev. *C
Page 2 of 12
FailSafe Function
The CY23FS04 is targeted at clock distribution applications
that could or which currently require continued operation
should the main reference clock fail. Existing approaches to
this requirement have utilized multiple reference clocks with
either internal or external methods for switching between
references. The problem with this technique is that it leads to
interruptions (or glitches) when transitioning from one
reference to another, often requiring complex external circuitry
or software to maintain system stability. The technique imple-
mented in this design completely eliminates any switching of
references to the PLL, greatly simplifying system design.
The CY23FS04 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to reference via the
external feedback loop. This is accomplished by utilizing a
digitally controlled capacitor array to pull the crystal frequency
over an approximate range of +300 ppm from its nominal
frequency.
Notes:
1. For normal operation, connect either one of the four clock outputs to the FBK input.
2. Weak pull-downs on all outputs
3. Weak pull-ups on these inputs.
4. Weak pull-down on these inputs.
Pin Definition
Pin Number
Pin Name
Description
1,2
REF[1:2]
Reference clock inputs. 5V-tolerant[4].
3,4
CLKB[1:2]
Bank B clock outputs.[1,2]
14,13
CLKA[1:2]
Bank A clock outputs.[1,2]
15
FBK
Feedback input to the PLL.[1,4]
12,5
S[1:2]
Frequency select pins and PLL and DCXO bypass mode.[3]
8XIN
Reference crystal input.
9XOUT
Reference crystal output.
10
FAIL#/SAFE
Valid reference indicator. A high level indicates a valid reference input.
11
VDD
2.5V or 3.3V power supply.
7
VDDC
3.3V power supply.
6
VSS
Ground.
16
REFSEL
Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL
= 1, REF1 is selected, REFSEL = 0, REF2 is selected.
Table 1. Configuration Table
S[2:1]
XTAL (MHz)
REF (MHz)
OUT (MHz)
REF:OUT ratio
REF:XTAL
ratio
Out:XTAL
ratio
Min.
Max.
Min.
Max.
Min.
Max.
00
PLL and DCXO Bypass Mode
01
8.33
30.00
4.17
15.00
4.17
15.00
x1
1/2
1/2
10
8.00
25.00
16.00
50.00
16.00
50.00
x1
2
2
11
8.33
28.33
50.00
170.00
50.00
170.00
x1
6
6
RE F
OU T
Fa i l # / S a f e
t
FS L
t
FS H
Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically
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