CY23FP12-002
Document #: 38-07644 Rev. **
Page 7 of 10
Switching Characteristics for CY23FP12-002SC/I [5]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Reference Frequency[6]
10
200
MHz
Reference Edge Rate
1
V/ns
Reference Duty Cycle
25
75
%
t1
Output Frequency[7]
CL = 15 pF, Commercial Temperature
10
200
MHz
CL = 15 pF, Industrial Temperature
10
166.7
CL = 30 pF, Commercial Temperature
10
100
CL = 30 pF, Industrial Temperature
10
83.3
Duty Cycle[5]
VDDA/B = 3.3V, measured at VDD/2
45.0
50.0
55.0
%
VDDA/B = 2.5V
40.0
50.0
60.0
t3
Rise Time[5]
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 30 pF (standard drive and high drive)
1.6
ns
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 15 pF (standard drive and high drive)
0.8
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
2.0
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
1.0
t4
Fall Time[5]
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 30 pF (standard drive and high drive)
1.6
ns
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 15 pF (standard drive and high drive)
0.8
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
1.6
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
0.8
TTB
Total Timing Budget,[8,9]
Bank A and B same
frequency
Outputs @200 MHz, tracking skew not
included
650
ps
Total Timing Budget, Bank
A and B different frequency
850
t5
Output to Output Skew[5]
All outputs equally loaded
200
ps
Bank to Bank Skew
Same frequency
200
Bank to Bank Skew
Different frequency
400
Bank to Bank Skew
Different voltage, same frequency
400
t6
Input to Output Skew (static
phase offset)[5]
Measured at VDD/2, REF to FBK
0
250
ps
t7
Device to Device Skew[5]
Measured at VDD/2
0
500
ps
tJ
Cycle to Cycle Jitter[5]
(Peak-to-peak)
Bank A and B same frequency
200
ps
Cycle to Cycle Jitter[5]
(Peak-to-peak)
Bank A and B different frequency
400
Notes:
5.
All parameters are specified with loaded outputs.
6.
When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto power-
down disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
7.
When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the output frequency can be as low as DC level.
8.
Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9.
TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply
voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output
skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.