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CY22E016L
Document Number: 001-06727 Rev. *D
Page 9 of 14
Hardware STORE Cycle
Parameter
Description
CY22E016L
Unit
Min
Max
tSTORE
[6]
STORE Cycle Duration
10
ms
tDELAY
[10]
Time Allowed to Complete SRAM Cycle
1
ms
tRESTORE
[11]
Hardware STORE High to Inhibit Off
700
ns
tHLHX
Hardware STORE Pulse Width
15
ns
tHLBL
Hardware STORE Low to STORE Busy
300
ns
Switching Waveforms
Figure 6. SRAM Read Cycle Number 1: Address Controlled [3, 5, 12]
Figure 7. SRAM Read Cycle Number 2: CE Controlled [3,12]
tRC
tAA
tOH
ADDRESS
DQ (DATA OUT)
DATA VALID
ADDRESS
tRC
CE
tACE
tLZCE
tPD
tHZCE
OE
tDOE
tLZOE
tHZOE
DATA VALID
ACTIVE
STANDBY
tPU
DQ (DATA OUT)
ICC
Notes
10. Read and Write cycles in progress before HSB are given this amount of time to complete.
11. tRESTOREis only applicable after tSTORE is complete.
12. HSB must remain HIGH during READ and WRITE cycles.
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