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CY9C62256-70ZI Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY9C62256-70ZI
Description  32K x 8 Magnetic Nonvolatile CMOS RAM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY9C62256-70ZI Datasheet(HTML) 4 Page - Cypress Semiconductor

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PRELIMINARY
CY9C62256
Document# : 38-15001 Rev. *F
Page 4 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–40°C to +85°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
except in case of Super Voltage pin (A9) while accessing 64
device ID and Silicon signature Bytes.........
−0.5V to VCC + 2.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Maximum Exposure to Magnetic Field
@ Device Package[2,3] ............................................ < 20 Oe
Operating Range
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
5V
± 10%
Industrial
–40°C to +85°C
5V
± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
CY9C62256-70
Unit
Min.
Typ.[5]
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
2.4
V
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.5V
V
VIL
Input LOW Voltage
–0.5[1]
0.8
V
IIX[4]
Input Leakage Current
GND < VI < VCC
–0.5
+0.5
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–0.5
+0.5
µA
ICC
VCC Operating Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
60
mA
ISB1
Automatic CE
Power-down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
500
µA
ISB2
Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC,
CE > VCC − 0.3V
VIN > VCC − 0.3V
or VIN < 0.3V, f = 0
90
µA
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
6pF
COUT
Output Capacitance
8
pF
Notes:
1. VIL (min.) = –2.0V for pulse duration of 20 ns.
2. Magnetic field exposure is highly dependent on the distance from the magnetic field source. The magnetic field falls off as 1/R squared, where R is the distance
from the magnetic source.
3. Exposure beyond this level may cause loss of data.
4. IIX during access to 64 device ID and silicon signature bytes with super voltage pin at VCC + 2.0V will be 100 µA max.
5. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
6. Tested initially and after any design or process changes that may affect these parameters.


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