CY22E016L
Document Number: 001-06727 Rev. *D
Page 3 of 14
Device Operation
The CY22E016L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a non-volatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the non-volatile cell (the STORE
operation) or from the non-volatile cell to SRAM (the RECALL
operation). This unique architecture enables storage and recall
of all cells in parallel. During the STORE and RECALL opera-
tions, SRAM READ and WRITE operations are inhibited. The
CY22E016L supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the non-volatile cells and up to one million STORE operations.
SRAM Read
The CY22E016L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–10 determines which of the 2,048 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of tAA (READ cycle 1). If the
READ is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time without the need for transitions on any control input pins,
and remains valid until another address change or until CE or OE
is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable prior to entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
IO0–7 is written into the memory if it is valid tSD, before the end
of a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation
During normal AutoStore operation, the CY22E016L draws
current from VCC to charge a capacitor connected to the VCAP
pin. This stored charge is used by the chip to perform a single
STORE operation. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part automatically disconnects the
VCAP pin from VCC and initiates a STORE operation.
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor,
having a capacity of between 68
μF and 220 μF (±20%) rated at
6V, is provided. In system power mode, both VCC and VCAP are
connected to the +5V power supply without the 68
μF capacitor.
In this mode, the AutoStore function of the CY22E016L operates
on the stored system charge as power goes down. The user
must, however, guarantee that VCC does not drop below 3.6V
during the 10 ms STORE cycle..
Figure 1. AutoStore Mode
Figure 2. System Power Mode
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