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CD74HCT40103M Datasheet(PDF) 7 Page - Texas Instruments

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Part No. CD74HCT40103M
Description  High-Speed CMOS Logic 8-Stage Synchronous Down Counters
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HCT40103M Datasheet(HTML) 7 Page - Texas Instruments

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7
MR to TC
tPLH,
tPHL
CL = 50pF
4.5
-
-
55
-
69
-
83
ns
CL = 15pF
5
-
23
-
-
-
-
-
ns
Output Transition Time
tTHL,tTLH
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
CP Maximum Frequency
fMAX
CL = 15pF
5
-
25
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-5
-
27
-
-
-
-
-
pF
NOTES:
3. Noncascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enables (PE or TE)-to-clock SET
UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC de-
vices:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = VCC
2 f
i + CL VCC
2 f
o where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage, fo = Output Frequency.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO
85oC
-55oC TO
125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
C
P fMAX
1
CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1
60
30
0
++
-----------------------------
11MHz
==
Timing Diagrams
FIGURE 1.
CP
MR
TE
PE
PL
P0
P1
P2
P3
P4
P5
P6
TC
P7
HC/HCT40103 COUNT
255 254
3
2
1
0
255 254 254 253
8
7
6
5
4
255
254 253
252
CD54HC40103, CD74HC40103, CD74HCT40103


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