CY14B101K
Document Number: 001-06401 Rev. *G
Page 8 of 24
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the timeout interrupt by setting WDS bit to ‘1’
before the counter reaching ‘0’. This reloads the counter with the
watchdog timeout value and restarts. As long as the user sets
the WDS bit before the counter reaches the terminal value, the
interrupt and flag never occur.
Write new timeout values by setting the watchdog WRITE bit to
‘0’. When the WDW is ‘0’ (from the previous operation), new
writes to the watchdog timeout value bits D5–D0 enable to
modify the timeout value. When WDW is a ‘1’, writes to bits D5
– D0 are ignored. The WDW function enables a user to set the
WDS bit without concern that the watchdog timer value is
modified. A logical diagram of the watchdog timer is shown in
Figure 4. Note that setting the watchdog timeout value to ‘0’ is
otherwise meaningless and disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to timeout. The flag is set upon a
watchdog timeout and cleared when the Flags/Control register is
Read by the user. If the watchdog timeout occurs, the user can
also enable an optional interrupt source to drive the INT pin.
Power Monitor
The CY14B101K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to various
thresholds.
As described in the “AutoStore Operation” on page 3, when
VSWITCH is reached as VCC decays from power loss, a data store
operation is initiated from SRAM to the nonvolatile elements,
securing the last SRAM data state. Power is also switched from
VCC to the backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source, no data is read or
written and the clock functions are not available to the user. The
clock continues to operate in the background. Updated clock
data is available to the user after VCC is restored to the device
and the RECALL delay (see the section “AutoStore/Power Up
RECALL” on page 16).
Interrupts
The CY14B101K provides three potential interrupt sources.
They include the watchdog timer, the power monitor, and the
clock or calendar alarm. Individually enable each and assign to
drive the INT pin. In addition, each has an associated flag bit that
the host processor uses to determine the cause of the interrupt.
Some of the sources have additional control bits that determine
functional behavior. In addition, the pin driver has three bits that
specify its behavior when an interrupt occurs.
The three interrupts each have a source and an enable. Both the
source and the enable are active (true HIGH) to generate an
interrupt output. Only one source is necessary to drive the pin.
The user identifies the source by reading the Flags/Control
register, that contains the flags associated with each source. All
flags are cleared to ‘0‘ when the register is READ. The flags are
cleared only after a complete read cycle (WE HIGH). The power
monitor has two programmable settings that is explained in the
section “Power Monitor” on page 8.
Once an interrupt source is active, the pin driver determines the
behavior of the output. It has two programmable settings as
shown in the following section. Pin driver control bits are located
in the Interrupts register.
According to the programming selections, the pin is driven in the
backup mode for an alarm interrupt. In addition, the pin is an
active LOW (open drain) or an active HIGH (push pull) driver. If
programmed for operation during backup mode, it is only active
LOW. Lastly, the pin provides a one shot function so that the
active condition is a pulse or a level condition. In one shot mode,
the pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In level mode,
the pin goes to its active polarity until the Flags/Control register
is read by the user. This mode is used as an interrupt to a host
microcontroller. The Interrupt register is initialized to 00h. The
control bits are summarized as follows:
Watchdog Interrupt Enable – WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog timeout occurs. When WIE is set to ‘0’, the watchdog
timer affects only the internal flag.
Alarm Interrupt Enable – AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When set to ‘0’, the alarm
match only affects the internal flag.
Power Fail Interrupt Enable – PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When set to ‘0’,
the power fail monitor affects only the internal flag.
High/Low – H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when VCC > VSWITCH. When set to a ‘0’, the INT pin is active
LOW and the drive mode is open drain. Active LOW (open drain)
is operational even in battery backup mode.
Pulse/Level – P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags/Control register is READ.
Figure 4. Watchdog Timer Block Diagram
1 Hz
Oscillator
Clock
Divider
Counter
Zero
Compare
WDF
WDS
Load
Register
WDW
D
Q
Q
Watchdog
Register
write to
Watchdog
Register
32 Hz
32,768 KHz
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