PRELIMINARY
Linear Power PSoC™ Devices
CY8C41123 and CY8C41223
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134
•
408.943.2600
Document 001-00360 Rev. *A
Revised November 17, 2005
1.0 Features
1.1
Key Features
• Extended Operating Voltage of 2.5V to 36V
• 2 HV Linear Opamp Control Loops for Driving Power PFETs
• 2 HV Analog Sense Inputs
• 4KB of Flash
• 256 Bytes of SRAM
1.2
Improved Features
• Very Low Current Mode for 100 nA Sleep (Deep Sleep)
• Analog Absolute Accuracy (0.75%)
• Additional Flexibility for Sleep Modes
• 2 Comparators with DAC References
• 6- to 12-Bit ADC (20 Ksps at 8 Bits)
• Configurable Analog Mux, 10:1 or 5:2 Differential
• Configurable Digital Blocks
— 8- to 16-Bit Timers and Counters
— Connectable to All GPIO Pins
— Digital Blocks can Drive Outputs to 36V
— Complex Peripherals by Combining Blocks
1.3
Applications
• Battery Chargers (Linear or Fly Back)
• White LED Drivers
• Temperature Sensor (Thermistor, Thermocouple)
2.0
Block Diagram
Figure 2-1. Block Diagram
DIGITAL SYSTEM
1DigitalRow
System Bus
SYSTEMRESOURCES
PSoCCORE
M8CCPU
256BSRAM
4KBFlash
GDO1
HVdd
POR andLVD
SystemResets
InterruptController
DigitalPSoC BlockArray
DBC00
DBC01
DBD02
DBD03
PSoCCORE
Internal
Voltage
Reference
LowSpeed
Oscillator
I2C
Digital
Clocks
Internal
Main
Oscillator
GlobalDigitalInterconnectBus
Atten0
Atten1
AMuxBus0
AMuxBus1
AMuxBus2
AMuxBus3
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
ODAC0
ODAC1
VDAC0
ODAC0
VBG
IBIAS
VDAC0
VDAC1
ODAC1
VDAC1
VS1
GDO0
VS0
InternalVdd
ANALOG and HIGH VOLTAGE
SECTIONS
LowDrop-Out
Regulator
COMP1
COMP0
SleepandWatchdog
Analogto
Digital
Convertor
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