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CY8C41123 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY8C41123
Description  Linear Power PSoC??Devices
Download  36 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C41123 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY8C41123 and CY8C41223
PRELIMINARY
Document 001-00360 Rev. *A
Page 7 of 36
6.0
Pin Assignment
This section lists, describes, and illustrates all Linear Power PSoC device pins and pinout configurations. For up-to-date ordering,
pinout, and packaging information, go to http://www.cypress.com/psoc.
6.1
Pinouts
PSoC devices are available in a variety of packages. Refer to the following information for details on individual devices. Every
port pin (labeled with a “P”) in the following tables and illustrations is capable of digital IO.
6.1.1
8-Pin SOIC Part Pinouts
The 8-pin SOIC part is for the CY8C41123 PSoC device.
6.1.2
16-Pin SOIC Part Pinouts
The 16-pin SOIC part is for the CY8C41223 PSoC device.
8-Pin Part Pinout (SOIC)
Pin
No.
Name
Description
CY8C41123 PSoC Device
1
HVO
GD1
High Side Linear Gate Driver 1
2
IO
I
P0[1]
3
IO
I
P1[1]
I2C Clock*
4
Power
Vss
Ground Connection
5
IO
I
P1[0]
I2C Data*
6
IO
I
P0[0]
7
HVI
VS0
High Voltage Sense 0
8
Power
HVdd
Supply Voltage
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage.
* These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
16-Pin Part Pinout (SOIC)
Pin
No.
Name
Description
CY8C41223 PSoC Device
1
HVO
GD1
High Side Linear Gate Driver 1
2
HVI
VS1
High Voltage Sense 1
3
IO
I
P0[7]
I2C Clock
4
IO
I
P0[5]
I2C Data
5
IO
I
P0[3]
6
IO
I
P0[1]
7
IO
I
P1[1]
I2C Clock*
8
Power
Vss
Ground Connection
9
IO
I
P1[0]
I2C Data*
10
IO
I
P0[0]
11
IO
I
P0[2]
Optional External CLK Input (EXTCLK)
12
IO
I
P0[4]
13
IO
I
P0[6]
14
HVI
VS0
High Voltage Sense 0
15
HVO
GD0
High Side Linear Gate Driver 0
16
Power
HVdd
Supply Voltage
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage.
* These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
SOIC
1
2
3
4
8
7
6
5
VS0
P0[0]
P1[0] I2C*
GD1
P0[1]
I2C* P1[1]
Vss
HV
dd
SOIC
HV
dd
GD0
VS0
P0[6]
P0[4]
P0[2], EXTCLK
P0[0]
P1[0], I2C*
16
15
14
13
12
11
1
2
3
4
5
6
7
8
GD1
VS1
SCL, P0[7]
SDA, P0[5]
P0[3]
I2C*, P1[1]
Vss
10
9
P0[1]


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