CY8C20534, CY8C20434
CY8C20334, CY8C20234
Document Number: 001-05356 Rev. *D
Page 2 of 34
PSoC Functional Overview
The PSoC® family consists of many Mixed Signal Arrays with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU based system components
with one low cost single chip programmable component. A
PSoC device includes configurable analog and digital blocks
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 1, is comprised of three main areas: the Core, the Sys-
tem Resources, and the CapSense Analog System. A common
versatile bus enables connection between IO and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control cir-
cuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the MCU and analog
mux.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO (Internal
Main Oscillator), and ILO (Internal Low speed Oscillator). The
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architec-
ture microprocessor.
System Resources provide additional capability such as a con-
figurable I2C slave or SPI master-slave communication inter-
face and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.8V analog reference. Together they support
capacitive sensing of up to 28 inputs.
The CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware per-
forms capacitive sensing and scanning without requiring exter-
nal components. Capacitive sensing is configurable on each
GPIO pin. Scanning of enabled CapSense pins is completed
quickly and easily across multiple ports.
Figure 1. Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are con-
nected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive mea-
surement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces such as sliders and
touch pads
■ Chip-wide mux that enables analog input from any IO pin
■ Crosspoint connection between any IO pin combinations
When designing capacitive sensing applications, refer to the lat-
est signal-to-noise signal level requirements Application Notes,
found
under
http://www.cypress.com
>>
DESIGN
RESOURCES >> Application Notes. In general, unless other-
wise noted in the relevant Application Notes, the minimum sig-
nal-to-noise ratio (SNR) requirement for CapSense applications
is 5:1.
ID AC
R eferenc e
Buffer
Vr
C internal
C ap Sens e C ounters
C om parator
Mu x
Mu x
Refs
C apSens e
Cloc k Select
Relaxation
O s c illator
(RO)
CSC LK
IMO
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