CY7C68300A
This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
Document #: 38-08031 Rev. *E
Page 5 of 21
3.2
Additional Pin Descriptions
3.2.1
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB.
3.2.2
SCL, SDA
The clock and data pins for the I2C-compatible port should be
connected to your configuration EEPROM and to VCC through
2.2k resistors.
3.2.3
XTALIN, XTALOUT
The CY7C68300A requires a 24-MHz signal to derive internal
timing. Typically a 24-MHz parallel-resonant fundamental
mode crystal is used, but a 24-MHz square wave from another
source can also be used. If a crystal is used, connect the pins
to XTALIN and XTALOUT, and also through 20-pF capacitors
to GND. If an alternate clock source is used, apply it to XTALIN
and leave XTALOUT open.
3.2.4
ATA_EN
ATA_EN allows bus sharing with other host devices. Setting
ATA_EN = 1 enables the ATA interface for normal operation.
Setting ATA_EN = 0 disables (High-Z) the ATA interface pins
and removes the CY7C68300A from the USB. Because the
CY7C68300A supports a true low-power USB suspend state,
new functionality was added to ensure that transitions of the
ATA_EN signal could be detected properly under all circum-
stances. The CY7C68300A will behave in the following
manner:
• If ATA_EN transitions to '0' during normal operation, the
CY7C68300A will disconnect from the USB and drop to a
low-power mode.
• If ATA_EN transitions to '1' when in low-power mode and
no other condition is causing the low-power state, the
CY7C68300A will return to a post-reset state and reconnect
to the USB.
• If the CY7C68300A is already in suspend and ATA_EN
transitions to '0', the CY7C68300A will resume only long
enough to stop driving the ATA interface (High-Z) and drop
back to low-power again.
• If the CY7C68300A is already in suspend and ATA_EN
transitions to '1', the CY7C68300A will resume only long
enough to start driving the ATA interface and drop to low-
power again.
Note:
2.
A # sign after the signal name indicates that it is an active LOW signal.
46
39
VBUS_PW
R_VALID
I
Input
VBUS detection. Indicates to the CY7C68300A that VBUS
power is present.
47
40
ARESET# O/Z[1]
ATA Reset.
48
41
GND
GND
Ground.
49
42
RESET#
I
Active LOW Reset. Resets the entire chip. This pin is normally
tied to VCC through a 100K resistor, and to GND through a
0.1-µF capacitor, supplying a 10-ms reset.
50
43
VCC
PWR
VCC. Connect to 3.3V power source.
51
44
ATA_EN
I
Input – If CY7C68300A is not
in mfg mode, polled every 20
ms after start-up. If LOW,
SSOP pins 36–38, 41–45
and 47 or QFN pins 29–31,
34–38 and 40 are three-
stated.
Active HIGH. ATA interface enable. Allows ATA bus sharing
with other host devices. Setting ATA_EN = 1 enables the ATA
interface for normal operation. Disabling ATA_EN three-states
(High-Z) the ATA interface and halts the ATA interface state
machine logic.
52
45
DD8
I/O[1] Hi-Z
ATA Data bit 8.
53
46
DD9
I/O[1] Hi-Z
ATA Data bit 9.
54
47
DD10
I/O[1] Hi-Z
ATA Data bit 10.
55
48
DD11
I/O[1] Hi-Z
ATA Data bit 11.
56
49
DD12
I/O[1] Hi-Z
ATA Data bit 12.
Pin Descriptions (continued)
SSOP
Pin
QFN
Pin
Pin Name
Pin
Type
Default State at Start-up
Pin Description
24MHz crystal
20pF
20pF
Figure 3-3. XTALIN, XTALOUT Diagram
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