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1K/4K/16K x36/x18/x2 Tri Bus FIFO
CY7C43646
CY7C43666
CY7C43686
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06023 Rev. *C
Revised September 26, 2003
Features
• High-speed, low-power, first-in first-out (FIFO) memo-
ries w/ three independent ports (one bidirectional x36,
and two unidirectional x18)
• 1K x36/x18x2 (CY7C43646)
• 4K x36/x18x2 (CY7C43666)
• 16K x36/x18x2 (CY7C43686)
• 0.35-micron CMOS for optimum speed/power
• High speed 133-MHz operation (7.5-ns read/write
cycle times)
•Low power
—ICC= 100 mA
—ISB= 10 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT mode user-selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Timing
Mode
Status
Flag Logic
Read
Pointer
Write
Pointer
1K/4K/16K
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail2
Register
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0−35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFC/IRC
AFC
BE/FWFT
B0−17
CLKB
CSB
RENB
MBB
SIZEB
RTI
EFB/ORB
AEB
MBF1
Common
Port Logic
(B and C)
BE
C0−17
Port C
Control
Logic
CLKC
WENC
MBC
SIZEC
Flag Offset
Registers
x36
CY7C43666 CY7C436461K/4K/16K x36/x18/x2 Tri Bus FIFO
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