10 / 26 page
PRELIMINARY
CY7C60445, CY7C6045x
Document Number: 001-12395 Rev. *E
Page 10 of 26
Register Reference
The section discusses the registers of the enCoRe V LV device.
It lists all the registers in mapping tables, in address order.
Register Conventions
The register conventions specific to this section and the
Register Reference chapter are listed in the following table.
Register Mapping Tables
The enCoRe V LV device has a total register address space of
512 bytes. The register space is also referred to as IO space and
is broken into two parts: Bank 0 (user space) and Bank 1 (config-
uration space). The XIO bit in the Flag register (CPU_F) deter-
mines which bank the user is currently in. When the XIO bit is
set, the user is said to be in the “extended” address space or the
“configuration” registers.
Register Map Bank 0 Table: User Space
Table 3. Register Conventions
Convention
Description
R
Read register or bits
W
Write register or bits
O
Only a read/write register or bits
L
Logical register or bits
C
Clearable register or bits
#
Access is bit specific
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
PRT0DR
00
RW
40
80
C0
PRT0IE
01
RW
41
81
C1
02
42
82
C2
03
43
83
C3
PRT1DR
04
RW
44
84
C4
PRT1IE
05
RW
45
85
C5
06
46
86
C6
07
47
87
C7
PRT2DR
08
RW
48
88
I2C_XCFG
C8
RW
PRT2IE
09
RW
49
89
I2C_XSTAT
C9
R
0A
4A
8A
I2C_ADDR
CA
RW
0B
4B
8B
I2C_BP
CB
R
PRT3DR
0C
RW
4C
8C
I2C_CP
CC
R
PRT3IE
0D
RW
4D
8D
CPU_BP
CD
RW
0E
4E
8E
CPU_CP
CE
R
0F
4F
8F
I2C_BUF
CF
RW
PRT4DR
10
RW
50
90
CUR_PP
D0
RW
PRT4IE
11
RW
51
91
STK_PP
D1
RW
12
52
92
D2
13
53
93
IDX_PP
D3
RW
14
54
94
MVR_PP
D4
RW
15
55
95
MVW_PP
D5
RW
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
D9
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK2
DE
RW
1F
5F
9F
INT_MSK1
DF
RW
20
60
A0
INT_MSK0
E0
RW
21
61
A1
INT_SW_EN
E1
RW
22
62
A2
INT_VC
E2
RC
23
63
A3
RES_WDT
E3
W
Gray fields are reserved and should not be accessed.
# Access is bit specific.
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