CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B
Page 6 of 39
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X4 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW,
the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Reset must be performed on the FIFO after power up, before
data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X4 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Partial
Reset inputs can switch asynchronously to the clocks. A
Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the
Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Partial Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of big or little
endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long-word size, the Big Endian function has
no application and the BE input is a “Don’t Care”.)
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long word written to Port A will be transferred to Port B first;
the least significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to Port A as the most significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the least significant byte (word)
of the long word.
A LOW on the BE/FWFT input when the Master Reset (RST1
and RST2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the most significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to Port A as the least significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the most significant byte (word)
of the long-word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) mode.
Once the Master Reset (RST1, RST2) input is HIGH, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (MRS1,MRS2) input is HIGH, a LOW
on the BE/FWFT input during the second LOW-to-HIGH
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this
pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for
a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance state
when W/RA is HIGH.
W/RB
Port B
Write/Read
Select
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for
a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance state
when W/RB is LOW.
Pin Definitions (continued)
Signal Name
Description
I/O
Function
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