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CY7C43644-10AC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7C43644-10AC
Description  1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C43644-10AC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B
Page 4 of 39
B0–35
Port B Data
I/O
36-bit bidirectional data port for side B.
BE/FWFT
Big
Endian/First-
Word Fall-
Through
Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port B to
Port A the first word/byte written to Port B will come out as the most significant word/byte
on Port A. A LOW on BE will select Little Endian operation. In this case, the least signif-
icant byte or word on Port A is transferred to Port B first for A-to-B data flow. Similarly,
the fist word/byte written into Port B will come out as the least significant word/byte on
Port A for B-to-A data flow. After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode.
Once the timing mode has been selected, the level on this pin must be static throughout
device operation.
BM
Bus Match
Select (Port
A)
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and
can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and
can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A0–35 outputs, available
for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.[1]
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B0–35 outputs, available
for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.[1]
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FFA/IRA
Port A
Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B
Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
Pin Definitions (continued)
Signal Name
Description
I/O
Function


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