CY7C1522V18
CY7C1529V18
CY7C1523V18
CY7C1524V18
Document #: 38-05564 Rev. *D
Page 9 of 28
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII™/DDRII/QDRII+/DDRII+”.
Application Example[2]
Truth Table[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
L-H
L
L
D(A + 0) at K(t + 1)
↑ D(A + 1) at K(t + 1) ↑
Read Cycle:
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
L-H
L
H
Q(A + 0) at C(t + 1)
↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Notes:
2. The above application shows four DDR-II SIO being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
LD
#
R/W
#
B
W
#
Vt = VREF
CC#
CQ
CQ#
K#
ZQ
Q
D
K
CC# K
BUS
MASTER
(CPU
or
ASIC)
SRAM 1
SRAM 4
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R = 50 Ohms
R = 250 Ohms
CQ
CQ#
K#
ZQ
Q
LD
#
R/W
#
B
W
S
#
LD
#
R/W
#
Vt
Vt
Vt
R
R
R
A
A
D
R = 250 Ohms
B
W
S
#
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