PRELIMINARY
CY7C9925
Document #: 38-07688 Rev. **
Page 8 of 12
IIL
Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = 0.4V
–10
–
µA
IIHH
Input HIGH Current
(Test, FS, xFn)
VIN = VCC
–200
µA
IIMM
Input MID Current
(Test, FS, xFn)
VIN = VCC/2
–50
50
µA
IILL
Input LOW Current
(Test, FS, xFn)
VIN = GND
–
–200
µA
IOS
Short Circuit Current[8]
VCC = MAX, VOUT = GND (25° only)
–
–200
mA
ICCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max., All Input
Selects Open
–90
mA
–100
ICCN
Output Buffer Current per
Output Pair[9]
VCCN = VCCQ = Max., IOUT = 0 mA
Input Selects Open, fMAX
–14
mA
PD
Power Dissipation per
Output Pair[10]
VCCN = VCCQ = Max., IOUT = 0 mA
Input Selects Open, fMAX
–78
mW
Electrical Characteristics Over the Operating Range (continued)[5]
Parameter
Description
Test Conditions
Min.
Max.
AC Test Loads and Waveforms
AC Input Specifications
Parameter
Description
Condition
Min.
Max.
Unit
TR,TF
Input Rise/Fall Edge Rate
0.8V – 2.0V
–
10
ns/V
TPWC
Input Clock Pulse
HIGH or LOW
2
–
ns
TDCIN
Input Duty Cycle
PLL
10
90
%
Test Mode
30
70
FREF
Reference Input Frequency
FS=LOW
3.75
30
MHz
FS=MID
6.25
50
FS=HIGH
10
200[11]
Notes:
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
8. CY7C9925 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7C9925:ICCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F
∗ C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the
load circuit:
PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1
See note 9 for variable definition.
11. In test mode, Max REF input frequency is 133MHz.
TTL AC Test Load
TTL Input Test Waveform
VCC
R1
R2
CL
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns
≤1ns
2.0V
0.8V
Vth =1.5V
R1=100
R2=100
CL =30 pF
(Includes fixture and probe capacitance)
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