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CY7C4271-25AC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C4271-25AC
Description  16K/32K x 9 Deep Sync FIFOs
Download  18 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C4271-25AC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C4261
CY7C4271
Document #: 38-06015 Rev. *C
Page 7 of 18
Switching Characteristics Over the Operating Range
Parameter
Description
7C4261/71-10 7C4261/71-15 7C4261/71-25 7C4261/71- 35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tS
Clock Cycle Frequency
100
66.7
40
28.6 MHz
tA
Data Access Time
2
8
2
10
2
15
2
20
ns
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-up Time
3
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[12]
10
15
25
35
ns
tRSS
Reset Set-up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
25
35
ns
tOLZ
Output Enable to Output in Low Z[13]
000
0
ns
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[13]
37
38
3
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
20
ns
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.


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