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CY7C09159AV
CY7C09169AV
Document #: 38-06053 Rev. *B
Page 6 of 16
Switching Characteristics Over the Operating Range
Parameter
Description
CY7C09159AV
Unit
-9
-12
Min.
Max.
Min.
Max.
fMAX1
fMax Flow-Through
40
33
MHz
fMAX2
fMax Pipelined
67
50
MHz
tCYC1
Clock Cycle Time - Flow-Through
25
30
ns
tCYC2
Clock Cycle Time - Pipelined
15
20
ns
tCH1
Clock HIGH Time - Flow-Through
12
12
ns
tCL1
Clock LOW Time - Flow-Through
12
12
ns
tCH2
Clock HIGH Time - Pipelined
6
8
ns
tCL2
Clock LOW Time - Pipelined
6
8
ns
tR
Clock Rise Time
3
3
ns
tF
Clock Fall Time
3
3
ns
tSA
Address Set-up Time
4
4
ns
tHA
Address Hold Time
1
1
ns
tSC
Chip Enable Set-up Time
4
4
ns
tHC
Chip Enable Hold Time
1
1
ns
tSW
R/W Set-up Time
4
4
ns
tHW
R/W Hold Time
1
1
ns
tSD
Input Data Set-up Time
4
4
ns
tHD
Input Data Hold Time
1
1
ns
tSAD
ADS Set-up Time
4
4
ns
tHAD
ADS Hold Time
1
1
ns
tSCN
CNTEN Set-up Time
4
4
ns
tHCN
CNTEN Hold Time
1
1
ns
tSRST
CNTRST Set-up Time
4
4
ns
tHRST
CNTRST Hold Time
1
1
ns
tOE
Output Enable to Data Valid
10
12
ns
tOLZ
OE to Low Z
2
2
ns
tOHZ
OE to High Z
1
7
1
7
ns
tCD1
Clock to Data Valid - Flow-Through
20
25
ns
tCD2
Clock to Data Valid - Pipelined
9
12
ns
tDC
Data Output Hold After Clock HIGH
2
2
ns
tCKHZ
Clock HIGH to Output High Z
2
9
2
9
ns
tCKLZ
Clock HIGH to Output Low Z
2
2
ns
Port to Port Delays
tCWDD
Write Port Clock High to Read Data Delay
40
40
ns
tCCS
Clock to Clock Set-up Time
15
15
ns
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