3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
CY7C09159AV
CY7C09169AV
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-06053 Rev. *B
Revised September 6, 2005
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 8K x 9 organization (CY7C09159AV)
— 16K x 9 organization (CY7C09169AV)
• Three Modes
— Flow-Through
— Pipelined
—Burst
• Pipelined output mode on both ports allows fast 83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns (max.)
• 3.3V Low operating power
— Active = 135 mA (typical)
— Standby = 10
µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available
Notes:
1. A0−A12 for 8K; A0−A13 for 16K.
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
FT/PipeL
I/O0L−I/O8L
Control
A0−A12/13L
CLKL
ADSL
CNTENL
CNTRSTL
R/WR
1
0
0/1
CE0R
CE1R
OER
1
0/1
0
FT/PipeR
I/O0R−I/O8R
I/O
Control
A0−A12/13R
CLKR
ADSR
CNTENR
CNTRSTR
1
0
0/1
1
0/1
0
I/O
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
9
9
[1]
[1]
13/14
13/14
CY7C09159AV
CY7C09169AV3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
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