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CY7C1568V18-375BZXC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1568V18-375BZXC
Description  72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1568V18-375BZXC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Document Number: 001-06551 Rev. *E
Page 7 of 28
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin is connected directly to VDDQ that enables the minimum
impedance mode. This pin is not connected directly to GND or is left unconnected.
DOFF
Input
DLL Turn Off
− Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation is different from that listed in this datasheet. For normal operation, this pin
is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode
when the DLL is turned off. In this mode, the device is operated at a frequency of up to 167 MHz with
DDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Is tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Is tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Is tied to any voltage level.
VREF
Input
Reference
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Pin Definitions (continued)
Pin Name
IO
Pin Description
[+] Feedback


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