CY7C4225V-35ASC datasheet(11/20 Pages) CYPRESS

Part #	CY7C4225V-35ASC

Description	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

Download	20 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 20 page

CY7C4225V/4205V/4215V

CY7C4425V/4235V/4245V

Document #: 38-06029 Rev. *C

Page 11 of 20

Read Cycle Timing

Reset Timing[16]

Notes:

15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time

between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.

16. The clocks (RCLK, WCLK) can be free-running during reset.

17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

Switching Waveforms (continued)

tCLKH

tCLKL

NO OPERATION

tSKEW2

WEN

tCLK

tOHZ

tREF

RCLK

Q0–Q17

EF

REN

WCLK

OE

tOE

tENS

tOLZ

tA

tENH

VALID DATA

[15]

tRS

tRSR

Q0–Q17

RS

tRSF

OE = 1

OE = 0

REN,WEN,

LD

EF,PAE

FF,PAF,

HF

[17]

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CY7C4225V-35ASC Datasheet(PDF) 11 Page - Cypress Semiconductor

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