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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document #: 38-06012 Rev. *A
Page 7 of 20
Switching Waveforms
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Write Cycle Timing
tCLKH
tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN
tCLK
tDH
tWFF
tWFF
tENH
WCLK
D0 –D17
FF
REN
RCLK
4275V–8
[14]
Read Cycle Timing
tCLKH
tCLKL
NO OPERATION
tSKEW2
WEN
tCLK
tOHZ
tREF
tREF
RCLK
Q0 –Q17
EF
REN
WCLK
OE
tOE
tENS
tOLZ
tA
tENH
VALID DATA
4275V–9
[15]
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