10 / 16 page
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Document #: 38-06013 Rev. *B
Page 10 of 16
First Data Word Latency after Reset with Read and Write
Notes:
17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK
+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
D0(FIRST VALID WRITE)
tSKEW1
WEN1
WCLK
Q0 –Q8
EF
REN1,
REN2
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1
D2
D3
D4
D0
D1
D0 –D8
tA
WEN2
(if applicable)
[17]
[18]
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