64K/128K x 9 Deep Sync FIFOs
CY7C4281
CY7C4291
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06007 Rev. *C
Revised August 2, 2005
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64K × 9 (CY7C4281)
• 128K × 9 (CY7C4291)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
•Low power
—ICC = 40 mA
— ISB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Pin-compatible density upgrade to CY7C42X1
family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
• Pb-Free Packages Available
Functional Description
The CY7C4281/91 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1
Synchronous
FIFO
family.
Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0–8
RCLK
Q0–8
WEN1
WCLK
RS
OE
Dual Port
64K x 9
128K x 9
WEN2/LD
REN1 REN2
EF
PAE
PAF
FF
RAMARRAY
Logic Block Diagram
Pin Configuration
PLCC
D1
D0
RCLK
VCC
GND
WCLK
WEN2/LD
Q8
Q7
PAF
PAE
5
6
7
8
9
10
11
12
13
REN1
OE
REN2
4321
31 30
32
21
22
23
24
27
28
29
25
26
14 15 16 17 18 19 20
Q6
Q5
WEN1
RS
Top View
CY7C4281
CY7C4291
CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs
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