5 / 16 page
CY7C4281
CY7C4291
Document #: 38-06007 Rev. *C
Page 5 of 16
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
FF
FF
EF
EF
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
FULL FLAG (FF)# 1
CY7C4281/91
9
18
DATAIN (D)
RESET (RS)
9
RESET(RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
9
DATA OUT (Q)
918
Read Enable 2 (REN2)
CY7C4281/91
EMPTY FLAG (EF) #2
FULL FLAG (FF)# 2
Read Enable 2 (REN2)