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CY7C1480BV25-200AXC Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1480BV25-200AXC
Description  72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1480BV25-200AXC Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Document #: 001-15143 Rev. *D
Page 10 of 31
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a do not care for
the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Table 4. Truth Table
The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows.[3, 4, 5, 6, 7]
Operation
Add. Used
CE1
CE2
CE3 ZZ ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
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