36-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1416BV18, CY7C1427BV18
CY7C1418BV18, CY7C1420BV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-07033 Rev. *C
Revised September 27, 2007
Features
■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
■ 267 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 534 MHz) at 267 MHz for DDR-II
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Synchronous internally self-timed writes
■ DDR-II operates with 1.5 cycle read latency when DLL is
enabled
■ Operates as a DDR-I device with 1 cycle read latency in DLL
off mode
■ 1.8V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4V–VDD)
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both in Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1416BV18 – 4M x 8
CY7C1427BV18 – 4M x 9
CY7C1418BV18 – 2M x 18
CY7C1420BV18 – 1M x 36
Functional Description
The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and
CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1416BV18
and two 9-bit words in the case of CY7C1427BV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1416BV18 and
CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1418BV18 and two 36-bit words in the case of
CY7C1420BV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
267 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
267
250
200
167
MHz
Maximum Operating Current
x8
795
725
600
500
mA
x9
800
725
600
500
x18
835
760
620
525
x36
910
825
675
570
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
