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PRELIMINARY
CY7C1410V18
CY7C1425V18
CY7C1412V18
CY7C1414V18
Document #: 38-05592 Rev. **
Page 2 of 23
Logic Block Diagram (CY7C1410V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
21
8
16
8
NWS[1:0]
VREF
8
A(20:0)
21
C
C
8
Write
Reg
Write
Reg
CQ
CQ
8
DOFF
Logic Block Diagram (CY7C1425V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
9
18
9
BWS[0]
VREF
9
A(20:0)
21
C
C
9
Write
Reg
Write
Reg
CQ
CQ
9
DOFF