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CY7C1416JV18, CY7C1427JV18
CY7C1418JV18, CY7C1420JV18
Document Number: 001-12558 Rev. *C
Page 3 of 26
Logic Block Diagram (CY7C1418JV18)
Logic Block Diagram (CY7C1420JV18)
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS[1:0]
VREF
18
21
C
C
18
LD
Control
Burst
Logic
A0
A(20:1)
CQ
CQ
R/W
DOFF
20
18
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS[3:0]
VREF
36
20
C
C
36
LD
Control
Burst
Logic
A0
A(19:1)
CQ
CQ
R/W
DOFF
19
36
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