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CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *H
Page 2 of 31
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Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.0
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BWB
BWC
BWD
BWA
MEMORY
ARRAY
DQs
DQPA
DQPB
DQPC
DQPD
SLEEP
CONTROL
ZZ
A[1:0]
2
DQA ,DQPA
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQD ,DQPD
BYTE
WRITE DRIVER
Logic Block Diagram – CY7C1360C (256K x 36)