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CY7C1381CV25
CY7C1383CV25
Document #: 38-05241 Rev. *B
Page 2 of 35
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPA
DQPB
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
CONTROL
1
2
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A[1:0]
ZZ
DQs
DQPA
DQPB
DQPC
DQPD
A0, A1, A
ADV
CLK
ADSP
ADSC
BWD
BWC
BWB
BWA
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQA,
DQPA
BYTE
WRITE REGISTER
DQB,
DQPB
BYTE
WRITE REGISTER
DQC,
DQPC
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQD,
DQPD
BYTE
WRITE REGISTER
DQD,
DQPD
BYTE
WRITE REGISTER
DQC,
DQPC
BYTE
WRITE REGISTER
DQB,
DQPB
BYTE
WRITE REGISTER
DQA,
DQPA
BYTE
WRITE REGISTER
Logic Block Diagram – CY7C1381CV25 (512K
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE2
CE3
GW
BWE
A0,A1,A
BWB
BWA
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQPA
DQPB
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1383CV25 (1M x 18)
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