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CY7C1399D-10VXC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1399D-10VXC
Description  256K (32K x 8) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1399D-10VXC Datasheet(HTML) 1 Page - Cypress Semiconductor

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PRELIMINARY
256K (32K x 8) Static RAM
CY7C1399D
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05467 Rev. *C
Revised January 10, 2005
Features
• Pin- and function-compatible with CY7C1399B
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
•High speed
—tAA = 8 ns
• Low active power
—ICC = 60 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 1.2 mA (“L” Version only)
• Data Retention at 2.0V
• Available in 28-SOJ and 28-TSOP I Pb-Free packages
Functional Description[1]
The CY7C1399D is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tri-state drivers. The
device has an automatic power-down feature, reducing the
power consumption when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399D is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I Pb-Free packages.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
32K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A9
A0


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