CY7C1380CV25
CY7C1382CV25
Document #: 38-05240 Rev. *C
Page 6 of 33
CY7C1380CV25–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
P4,N4,
A2,B2,
C2,R2,
A3,B3,C3,
T3,T4,A5,B5,
C5,
T5,A6,B6,C6,R6
R6,P6,A2,
A10,B2,
B10,N6,P3,P4,
P8,P9,P10,
P11,R3,R4,R8,
R9,R10,R11
Input-
Synchronous
Address Inputs used to select one of the
address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and
CE1,CE2, andCE3[2]are sampled active. A1: A0
are fed to the two-bit counter..
BWA,BWB
BWC,BWD
93,94,95,
96
L5,G5,
G3,L3
B5,A5,A4,
B4
Input-
Synchronous
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
88
H4
B7
Input-
Synchronous
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
BWE
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
89
K4
B6
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
CE1
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on
the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
CE2[2]
97
-
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3[2]
92
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.Not connected
for BGA. Where referenced, CE3 is assumed
active throughout this document for BGA.
OE
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
ADSP
84
A4
B9
Input-
Synchronous
Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
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