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CY7C1917CV18-200BZXC Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1917CV18-200BZXC
Description  18-Mbit DDR-II SRAM 4-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1917CV18-200BZXC Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Document Number: 001-07161 Rev. *B
Page 11 of 31
Burst Address Table
(CY7C1319CV18, CY7C1321CV18)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Write Cycle Descriptions
The write cycle description table for CY7C1317CV18 and CY7C1319CV18 follows. [2, 8]
BWS0/
NWS0
BWS1/
NWS1
K
K
Comments
L
L
L–H
During the data portion of a write sequence
:
CY7C1317CV18
− both nibbles (D
[7:0]) are written into the device,
CY7C1319CV18
− both bytes (D
[17:0]) are written into the device.
L
L
L-H During the data portion of a write sequence
:
CY7C1317CV18
− both nibbles (D
[7:0]) are written into the device,
CY7C1319CV18
− both bytes (D
[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
:
CY7C1317CV18
− only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1319CV18
− only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
:
CY7C1317CV18
− only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1319CV18
− only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
:
CY7C1317CV18
− only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1319CV18
− only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
:
CY7C1317CV18
− only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1319CV18
− only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
L–H
No data is written into the devices during this portion of a write operation.
H
H
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1917CV18 follows. [2, 8]
BWS0
KK
L
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
No data is written into the device during this portion of a write operation.
H
L–H
No data is written into the device during this portion of a write operation.
Note
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
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