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CY7C1380CV25 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1380CV25
Description  18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Download  33 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1380CV25 Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1380CV25
CY7C1382CV25
Document #: 38-05240 Rev. *C
Page 9 of 33
GW
88
H4
B7
Input-
Synchronous
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on BWX
and BWE).
BWE
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
89
K4
B6
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
CE1
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled
on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the
device. ADSP is ignored if CE1 is HIGH.
CE2[2]
97
-
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled
on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the
device.
CE3 [2]
92
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled
on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the
device. Not available for AJ package
version.Not connected for BGA. Where refer-
enced, CE3 is assumed active throughout this
document for BGA.
OE
86
F4
B8
Input-
Asynchronou
s
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the
rising edge of CLK, active LOW. When
asserted, it automatically increments the
address in a burst cycle.
ADSP
84
A4
B9
Input-
Synchronous
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
85
P4
A8
Input-
Synchronous
Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
CY7C1382CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description


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